The present invention relates to a slew rate output circuit, and more particularly to a slew rate output circuit with an improved driving capability of driving an output MOS field effect transistor in a semiconductor integrated circuit.
In some fields of applications of the semiconductor integrated circuits, the slew rate function may be required. This slew rate function is to prevent rapid ON/OFF switching operations of the output transistor upon variation in voltage level of an input pulse signal, so as to reduce a variation speed of the waveform of the output signal. This slew rate function is capable of preventing appearance of noises on power lines or ground lines of MOS field effect transistor integrated circuits. This slew rate function is also capable of preventing appearances of overshoot and undershoot of the waveforms of the output signals. This slow rate function is also capable of causing drop of a flyback voltage of an inductance load.
FIG. 1 is a circuit diagram illustrative of one of the conventional slew rate output circuit of open drain type for driving an output MOS field effect transistor, wherein the output MOS field effect transistor Q0 has an n-channel type and has a source electrode connected through a load R.sub.L to a power voltage line V.sub.dd and a drain electrode connected to a ground line as well as has a gate electrode which is controlled by two constant currents IrH, I.sub.rL. A Circuit configuration of this conventional open drain type slew rate output circuit for driving an output MOS field effect transistor is as follows.
An output n-channel MOS field effect transistor Q0 is provided to be connected in series between a first power voltage line providing a first power voltage V.sub.dd and a ground line providing a ground potential, wherein a source electrode connected through a load R.sub.L to the first power voltage line V.sub.dd whilst a drain electrode connected to the ground line. The source electrode of the output n-channel MOS field effect transistor Q0 is connected to an output terminal, so that a voltage of the source is an output voltage Vout and a current through the load R.sub.L is an output current Iout. A series connection of p-channel and n-channel MOS field effect transistors Q1 and Q2 is provided to be connected in series between a second power voltage line providing a second power voltage V.sub.cc and the ground line providing the ground potential, wherein the p-channel MOS field effect transistor Q1 is connected through a first constant current source CS1 supplying a first constant current IrH to the second power voltage line providing the second power voltage V.sub.cc, whilst the n-channel MOS field effect transistor Q2 is connected through a second constant current source CS2 supplying a second constant current IrL to the ground line providing the ground potential. An intermediate point between the p-channel and n-channel MOS field effect transistors Q1 and Q2 is connected to a gate of the above output n-channel MOS field effect transistor Q0. A gate of the p-channel MOS field effect transistor Q1 is connected to an output side of a first invertor I1 which has an input side receiving an input pulse signal Vin so that the input pulse signal Vin is inverted by the first invertor I1 to be entered into the gate of the p-channel MOS field effect transistor Q1, whilst a gate of the n-channel MOS field effect transistor Q2 is connected to an output side of a second invertor I2 which has an input side receiving the above input pulse signal vin so that the input pulse signal Vin is inverted by the second invertor I2 to be entered into the gate of the n-channel MOS field effect transistor Q2.
Operations of the above conventional open drain type slew rate output circuit for driving the output MOS field effect transistor will be described. FIG. 2 is a diagram illustrative of waveforms of the conventional open drain type slew rate output circuit of FIG. 1
When the input pulse signal Vin is changed from a low level to a high level, the high level input pulse signal Vin is inverted by the first and second invertors I1 and I2 and made into the low level gate input signals to be entered into the gates of the p-channel and n-channel MOS field effect transistors Q1 and Q2, so that the p-channel MOS field effect transistor Q1 turns ON, whilst the n-channel MOS field effect transistor Q2 turns OFF, whereby the first constant current IrH is supplied through the first constant current source CS1 to the gate of the output n-channel MOS field effect transistor Q0. As a result, an input capacitance of the output n-channel MOS field effect transistor Q0 is charged so that a gate voltage level of the output n-channel MOS field effect transistor Q0 is gradually risen to the high level until the input capacitance of the output n-channel MOS field effect transistor Q0 is charged up thereby to render the output n-channel MOS field effect transistor Q0 turn ON, whereby the load R.sub.L is made conductive to the ground line and the output voltage level Vout is dropped toward the ground level. In FIG. 2, Vgate means the gate voltage level of the output n-channel MOS field effect transistor Q0.
When the input pulse signal Vin is changed from the high level to the low level, the low level input pulse signal Vin is inverted by the first and second investors I1 and I2 and made into the high level gate input signals to be entered into the gates of the p-channel and n-channel MOS field effect transistors Q1 and Q2, so that the p-channel MOS field effect transistor Q1 turns OFF, whilst the n-channel MOS field effect transistor Q2 turns ON, whereby the second constant current IrL is supplied through the second constant current source CS2 to the gate of the output n-channel MOS field effect transistor Q0. As a result, the input capacitance of the output n-channel MOS field effect transistor Q0 is discharged so that a gate voltage level of the output n-channel MOS field effect transistor Q0 is gradually fallen to the low level until the input capacitance of the output n-channel MOS field effect transistor Q0 is discharged down thereby to render the output n-channel MOS field effect transistor Q0 turn OFF, whereby the load R.sub.L is made non-conductive to the ground line and the output voltage level Vout is risen toward the high level.
A falling time of the output voltage level Vout of the slew rate output circuit depends upon a rising time of the gate voltage of the output n-channel MOS field effect transistor Q0. This rising time of the gate voltage of the output n-channel MOS field effect transistor Q0 further depends upon both the input capacitance of the output n-channel MOS field effect transistor Q0 and the first constant current IrH supplied through the first constant current source CS1. Therefore, the falling time of the output voltage level Vout of the slew rate output circuit or a turn-ON time depends upon both the input capacitance of the output n-channel MOS field effect transistor Q0 and the first constant current IrH supplied through the first constant current source CS1. This means that the falling time of the output voltage level Vout of the slew rate output circuit or the turn-ON time is controllable by controlling both the input capacitance of the output n-channel MOS field effect transistor Q0 and the first constant current IrH supplied through the first constant current source CS1.
A rising time of the output voltage level Vout of the slew rate output circuit depends upon a falling time of the gate voltage of the output n-channel MOS field effect transistor Q0. This falling time of the gate voltage of the output n-channel MOS field effect transistor Q0 further depends upon both the input capacitance of the output n-channel MOS field effect transistor Q0 and the second constant current IrL supplied through the second constant current source CS2. Therefore, the rising time of the output voltage level Vout of the slew rate output circuit or a turn-OFF time depends upon both the input capacitance of the output n-channel MOS field effect transistor Q0 and the second constant current IrL supplied through the second constant current source CS2. This means that the rising time of the output voltage level Vout of the slew rate output circuit or the turn-OFF time is controllable by controlling both the input capacitance of the output n-channel MOS field effect transistor Q0 and the second constant current IrL supplied through the second constant current source CS2.
Since the input capacitance of the output n-channel MOS field effect transistor Q0 provides influences to both the turn-OFF time and turn-ON time of the slew rate output circuit, the turn-ON time of the slew rate output circuit is controllable by controlling the first constant current IrH supplied through the first constant current source CS1, whilst the turn-OFF time of the slew rate output circuit is controllable by controlling the second constant current IrL supplied through the second constant current source CS2, thereby realizing the slew rate function of the conventional slew rate output circuit.
The above conventional slew rate output circuit is, however, engaged with the following problems. The waveform of the output voltage of the conventional slew rate output circuit or the turn-ON time and the turn-OFF time are controlled by the first and second constant currents IrH and IrL supplied through the first and second constant current sources CS1 and CS2 respectively, for which reason the increase in the falling time of the output voltage Vout of the conventional slew rate output circuit necessarily causes an increase in delay time of the turn-ON, whilst the increase in the rising time of the output voltage Vout of the conventional slew rate output circuit necessarily causes an increase in delay time of the turn-OFF time. Those are caused by the facts that if long charge and discharge times of the output n-channel MOS field effect transistor Q0 are set by the first and second constant currents IrH and IrL supplied through the first and second constant current sources CS1 and CS2 respectively, this means that long times are necessary for rendering the gate voltage Vgate of the output n-channel MOS field effect transistor Q0 reach turn-ON and turn-OFF threshold voltages thereof.
The definitions of the delay times in the turn-ON and the turnOFF as well as the slew rate will be described with reference to FIG. 2. The delay time in the turn-ON is defined to be a time tPDr necessary for rendering the output voltage Vout fall down to 90% of the high level from a point of time when the input pulse signal Vin has been changed from the low level to the high level. The delay time in the turn-OFF is defined to be a time tPDf necessary for rendering the output voltage Vout rise up to 10% of the high level from a point of time when the input pulse signal Vin has been changed from the high level to the low level. The slew rate is defined by gradients in rising up and falling down of the waveforms and given by the following formula. EQU SR={Vout(90%)-Vout(10%)}/{T(90%)-T(10%)}
where Vout(10%) is 10% level of the high voltage level, Vout(90%) is 90% level of the high voltage level, T(10%) is a point of time when the output voltage level Vout reaches 10% level of the high voltage level, and T(90%) is a point of time when the output voltage level Vout reaches 90% level of the high voltage level.
Whereas the definitions of the delay times in the turn-ON and the turn-OFF as well as the slew rate may alternatively be made on the basis of the output current Iout, in this application, the definitions are made as described above.
In the above circumstances, it had been required to develop a novel slew rate output circuit free from the above problems.